1. Field of the Invention
The present invention relates to a PLL (Phase Locked Loop) circuit. A PLL circuit is utilized as a reference clock generating circuit in a CPU (Central Processing Unit), and as a tuning circuit in a cellular telephone, among other things.
2. Description of Related Art
A PLL circuit is one that follows the frequency of a reference signal inputted from outside.
A PLL circuit uses a reference signal to generate an oscillation signal, and outputs this oscillation signal. Furthermore, a PLL circuit also compares this oscillation signal against the reference signal, and changes the frequency of the oscillation signal so that the phases of the two signals approximate one another. By and by, the frequency of the oscillation signal is made identical to the frequency of the reference signal. The state, wherein the frequencies of both signals are identical is referred to as a locked state. The time required from the start of comparing an output signal against a reference signal until a locked state is achieved is referred to as locking time.
When used as a tuning circuit or the like, it is desirable that the locking time of a PLL circuit be as short as possible. The shorter the locking time, the more rapidly a PLL circuit can imitate the frequency changes of a reference signal. To shorten locking time, the time constant of a PLL circuit can be made smaller. As is commonly known, a time constant xcfx84 is defined by xcfx84=RC, wherein R is resistance, and C is capacitance. To make the time constant of a PLL circuit smaller, for example, the resistance value of the filter inside the PLL circuit can be made smaller.
However, when the time constant of a PLL circuit is made smaller, the stability of operation of the PLL circuit is lost. For example, if the time constant is too small, there are cases, wherein the frequency of an oscillation signal is fixed in a state, in which same deviates round the frequency of a reference signal, and fails to converge with the reference signal frequency.
An object of the present invention is to provide a PLL circuit, wherein locking time is short, and operation is stable.
To achieve this object, a PLL circuit related to the present invention comprises means for detecting a phase difference between a reference signal and a feedback signal; means for supplying either a positive current or a negative current in accordance with a polarity of a phase difference, while making internal impedance smaller when the absolute value of a phase difference is large, and making internal impedance larger when the absolute value of a phase difference is small; means for outputting a control voltage signal, which changes in accordance with the supply quantity of a positive current and a negative current; and means for generating a frequency signal as an oscillation signal and a feedback signal, whose frequency is controlled using a control voltage signal.
Changing the impedance of a supply means in accordance with the absolute value of a phase difference between a reference signal and a feedback signal makes it possible to change the time constant of a PLL circuit in accordance with the absolute value of the phase difference thereof. A PLL circuit of the present invention operates at a small time constant when the absolute value of a phase difference is large, and operates at a large time constant when the absolute value of a phase difference is small. Therefore, a PLL circuit of the present invention achieves short locking time, and stable operation.